Clock tree synthesis

Basics of Clock Tree Synthesis:
The main idea is to balance the skew between endpoints. They are built with the following constraints.

1. Clock Skew: Difference between the clock arrival times.
2. Clock Latency: Max delay between the clock root and clock leaf.
3. Transition Time

• Clock buffers are usually bigger in size and have a shorter transition time as well as a more even rise and fall times.
• Clock nets are generally routed first and on higher metal layers with minimum detouring to give it the highest priority in routing.
• Few other clock tree related topics that will be covered subsequently are

Signal Integrity issues/Clock nets aggressor/clock shielding:
Clock nets due to their importance have to be protected from becoming either aggressors or victims in SI closure. They are generally shielded with vdd or gnd to prevent that.

1. Effective skew: Worst skew between two flops that are talking to each other. This is either equal to or lower than the worst skew.
2. Useful skew: This is a concept where the skew (Difference in arrival of the clock at the flops is used to improve setup violations.
3. Few links that have more detailed information about clock tree synthesis
4. OCV: On chip variation
5. Few links that have good information about clock tree