Fifo of digital electronics

Q. Given the following FIFO and rules, how deep does the FIFO needs to be to prevent underflowing or overflowing?
RULES:
1) frequency(clk_A) = frequency(clk_B) / 4
2) period(en_B) = period(clk_A) * 100
3) duty_cycle(en_B) = 25%

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Sol: The Q is completely wrong...
1) Underflow in a fifo cannot be prevented by depth calculation.
2) The calculation, the author has provided is unecessary for the question ;-)