Gate Level Simulation, Part - II

Gate level simulation is used in the late design phase to increase the level of confidence about a design implementation and to complement verification results created by static methods (formal verification and static timing analysis). In addition to the disadvantages of medium to long run times to simulate comprehensive vector sets on large designs, the coverage of potential functional and timing problems highly depends on the quality of the input stimulus and cannot be guaranteed in a practical way. In some cases, however, a gate level simulation can help to verify dynamic circuit behavior that cannot be accurately verified with static methods. For e.g. the start up and reset phase of a chip. To reduce the overall cycle time, only a minimum amount of vectors should be simulated using the most accurate timing model available (parasitics extracted from post-layout database).

Unit Delay Simulation:
The netlist after synthesis, but before routing does not yet contain the clock tree. It does not make sense to use SDF backannotation at this step, but gatelevel simulation may be used to verify the reset circuit, the scan chain or to get data for power estimation. If no backannotation is used, simulators should use Libraries which have the specified block containing timing args disabled and using distributed delays instead. The default delay for a storage element at 10 ps, for a combinatorial gate 1 ps and a clock gating cell 0 is the most secure possibility to run unit delay simulation, and process size and performance are optimized if the specify block is disabled.

Full Timing Simulation (With SDF):
Simulation is run by taking full timing delays from sdf. The SDF file is used to back annotate values for propagation delays and timing checks to the Ver-ilog gate level netlist.

Comments are greatly appreciated.