gates from mux's

OR gate from 2:1 MUX:
Assumptions:
's' is the select line for the mux.
'I0 and I1' be the input data lines of the mux.
'Z' be the ouput of the Mux.

a,b inputs of the OR gate.


method 1 >>
Connect the input b to the select line 's' of mux.
Connect input 'a' to the 'I0' line input of mux.
Connect the 'I1' line input of mux to LOGIC 1(VCC).
Now ur mux out 'z' will be "a or b"

method 2>>
in this method instead of connecting the I1 line of the mux to VCC, connect(short) it to the Select line "s" of mux.

XOR gate from 2:1 mux:
Connect input 'b' to select line.
Then connect 'a' to I0, and connect 'a' to I1 using an inverter ( negation of a to I1).

If u reverse, (inverted a to I0, and a to I1 , you will get XNOR operation.)