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A single stage Flip Flop [acting as a Synchronizer]. The absolute minimum a design should provide.
One stage may be enough, if the incoming data frequency is "slow", and the Flip Flop family is "fast".
If the chosen Flip Flop has time to resolve the metastable condition before the next clock tick, and
the output of the FF does not go to an asynchronous gate - the design may be solid.
The time between the two white lines in the diagram below defines the Metastability window.
The diagram above shows the flip flop clock and three possible times [zones] the data may arrive at the Flip Flop [FF]. Data 'Da' arrives and becomes stable before the clock edge. Data 'Db' arrives just before the clock edge violating the flip flops set-up time. data 'Dc' changes [or arrives after] the clock edge violating the hold time of the flip flop.
