Key points in Logic Design Timing

• In a synchronous design, all memory elements, flip-flops and latches, are synchronized be a master clock.
• A timing diagram is used to graphically describe what happens at each flip-flop or latch output on every clock cycle.
• Clock distribution circuits are designed to minimize the clock skew and jitter. Clock skew is point to point variation in the clock arrival time, while jitter is cycle to cycle variation.
• The critical path is the slowest logic path in the design.
• Flip-flops sample the input D and transfer it to the output Q at each rising or falling edge of the clock.
• The logic input D can not change during the set-up time before, and the hold time, after the clock edge.
• A set-up violation occurs when the input D arrives during or after the set-up time for the critical path under worst-case timing conditions. The usual fix for a set-up violation is to reduce the logic delay.
• A hold violation occurs when a signal races through two levels of logic, through the fastest path, before the hold time is over under best case timing conditions. The usual fix is to insert logic delay.
• Latches are level sensitive devices.
• Preventing set-up violations can be easier because latch D inputs can change while the clock is high. Exploiting this fact is called "cycle stealing".
• Preventing hold violations is much harder due to the inclusion of the clock high time. Thus latch-based designs are not recommended.
• Cell libraries are carefully characterized for timing. To calculate the delay through a cell library, you need to know the load capacitance.
• Timing analysis is performed during and after synthesis, and again before fabrication.