Negative hold time

Negative hold time is generally seen where a delay is already added in the data path inside the flop.

Assume the flop which foundry gives us as library part has ports named as CLK-port, Data-port. Now treat this as a wrapper. Inside this we have the real flop whose ports are CLK-in, data-in. CLK-port is connected directly to CLK-in, Data-port goes through some delay element (either buffer or routing whatever) to Data-in. So even if the actual flop has hold requirement of say 0.2ns, if the data delay element value is 0.5ns, the library will give spec as -0.3ns HOLD requirement for the above flop. This signifies even if the data changes 0.3ns before CLK, it an be still latched as
for the actual flop(inside wrapper) it will still meet 0.2ns HOLD. (data changes after 0.2ns from clk change).

Advantage:
The biggest advantage is less iteration after layout...easy and less painful synthesis (else HOLDfixing can be iterative process)

Disadvantage:
We pay the cost in bigger setup times for above flops.