Output Waveforms of {Digital Logic Metastability Index}

Output waveforms due to signal timing Da, Db, Dc
'Da' produces a normal output, as the data does not violate the Set-up or Hold time of the device [in relation to the clock].
Either 'Db' or 'Dc' may produce a metastable output forcing the output to stay undefined for a longer amount of time,
increasing the propagation delay of the Flip Flop

Five possible conditions exist:
One: No timing violation occurred, and the output moves to the appropriate state (high or low).
Two: A timing violation does occur, and the output oscillates between the valid states (for a long time), or until its needed.
Third: A timing violation does occur, and the output moves to the wrong state.
Forth: A timing violation does occur, and the propagation delay is increased. Causing the next device in the chain to see the wrong value.
Fifth: A timing violation does occur, and no meta-stable behavior occurs. The output moves to the correct state with no oscillation or increase in propagation delay. However this condition is problematic because the gamble is taken each time the device is clock. This condition may persist for thousands of clock cycles, but may fail on the next clock cycle. For a fail-safe design stay in condition one, any other condition will result in failure.