Verilog Awareness - Interview Questions

Q: Given the following Verilog code, what value of "a" is "displayed"?

always @(clk)
begin
a = 0;
a <= 1;
$display(a);
end

Q: Given the following snippet of Verilog code, draw out the waveforms for "clk" and "a".

always @(clk)
begin
a = 0;
#5 a = 1;
end

Q: What is the difference between the following two lines of Verilog code?

#5 a = b;
a = #5 b;

Q: Write Verilog to provide a divide-by-3 clock from the standard clock.

Q: What is the difference between:

c = foo ? a : b;

and

if (foo) c = a; else c = b;

Q: Using the given, draw the waveforms for the following (each version is separate, i.e. not in the same run):

reg clk;
reg a;
always #10 clk = ~clk;

(1) always @(clk) a = # 5 clk;
(2) always @(clk) a = #10 clk;
(3) always @(clk) a = #15 clk;

Now, change to a wire, and draw for:

(4) assign #5 a = clk;
(5) assign #10 a = clk;
(6) assign #15 a = clk;